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1. Jan. 8 T |
Introduction
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Ch1 (pp.1-48) |
HW1: Prob.1.1(for part b, use the Fig. on p.48), 1.3 |
R1(pp.1-23), R2(pp.1-27) |
2. Jan. 10 Th
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MOS Transistors (MOSTs) |
Ch3 (pp.51-78) |
HW2: Prob.3.1, 3.6, 3.14 |
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3. Jan. 15 T |
Short channel MOSTs |
Ch3 (pp.83-120) |
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R1(pp.25-52) R2(pp.129-154) |
4. Jan. 17 Th |
Modeling of MOSTs (SPICE), EKV model |
Ch4 (pp.125-150) |
HW3: Prob.4.1, 4.3 |
R2(pp.130-133) |
5. Jan. 22 T |
CMOS Inverters |
Ch6 (pp.153-175) |
HW4: Prob.6.2, 6.3
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6. Jan. 24 F |
Interconnects
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Ch6 (pp.176-196) |
HW5: Prob.6.8 |
R1(pp.151-161) |
7. Jan. 29 T |
Power, Energy Super buffer Design |
Ch6 (pp.196-208) |
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R1(pp.53-75) |
8. Jan. 31 Th |
Memories-DRAM
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Ch10(pp.213-247) |
HW6: Prob.10.1, 10.2 |
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9. Feb. 5 T |
Midterm Exam 1 |
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Project Proposal
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10. Feb. 7 Th |
Memories-SRAM
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Ch10(pp.247-263) |
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R1(pp.183-205, 233-247)) |
11. Feb.12 T |
NVMs (ROM, FLASH, FRAM, STT-RAM, PCRAM. RRAM |
Ch10(pp.263-287)
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HW6: Prob.10.3, 10.4, 10.6 |
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12. Feb.14 Th |
(NVM continued) Discussion on projects and organization |
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13. Feb.19 T |
LP CMOS Logic Circuits |
Ch11(pp.293-313) |
HW7: Prob.11.2, 11.4 |
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14. Feb.21 Th |
Pipelining, Parallel Processing, Adiabatic Circuits |
Ch11(pp.313-333) |
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R2(pp.642-647) |
15. Feb.26 T |
I/O Circuits, Clocking, Multiple Vdd and Level Shifting |
Ch13(pp.336-371) |
Prob.13.1, 13.3, 13.9 |
R1(pp.92-97)
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16. Feb.28 Th |
Ultra Low Power Design
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R1(289-315) R2(pp.618-630) |
17. Mar. 5 T |
2nd Half Midterm |
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R2(697-705, 739-749
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18. Mar. 7 Th |
More on Advanced Topics in LP
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R2(697-705, 739-749), etc. |
19. Mar.12 T |
Project Presentations |
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Submit written reports |
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20. Mar.14 Th |
Project Presentations |
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Submit Written Reports |
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FINAL scheduled on Mar. 22 (4-7 p.m.)
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Replaced by Project Presentations |
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*Textbook S. M. Kang, et al. CMOS Digital Integrated Circuits Analysis and Design,
UCSC version- UCSC version (2017)
#Ref.1 (R1) J. Rabaey, Low Power Design Essentials, Springer (2009)
#Ref.2 (R2) R. Sarpeshkar, Ultra Low Power Bioelectronics, Cambridge University Press (2013)